http://www.heise.de/newsticker/meldung/17232
http://www.ecs.com.tw/download/k7vza30.htm
PCI Master Bus Timeout determines the number of PCI clock cycles (in increments of 32 PCICLK cycles) the controller waits before disconnecting a device if the first data access is not completed. This option can often be used to resolve issues with data corruption on disks and crackling with soundcards.